The present invention is directed, in general, to telecommunications equipment and, more specifically, to a system and method for controlling the initialization and operation of a multi-processor communications system.
Information systems have evolved from centralized mainframe computer systems supporting a large number of users to distributed computer systems based on local area network (LAN) architectures. As the cost-to-processing-power ratios for desktop PCs and network servers have dropped precipitously, LAN systems have proved to be highly cost effective. As a result, the number of LANs and LAN-based applications has exploded.
A consequential development relating to the increased popularity of LANs has been the interconnection of remote LANs, computers, and other equipment into wide area networks (WANs) in order to make more resources available to users. However, a LAN backbone can transmit data between users at high bandwidth rates for only relatively short distances. In order to interconnect devices across large distances, different communication protocols have been developed. These include X.25, ISDN, frame relay, and ATM, among others.
Frame relay has proved to be one of the most popular communication protocols. Frame relay provides up to T3 level speeds (from 56 Kbps up to about 45 Mbps) using packet switching technology. It is optimized for the transfer of protocol-oriented data in packets of variable length. Data is sent in high-level data link control packets, called xe2x80x9cframesxe2x80x9d. A typical frame includes a xe2x80x9cheaderxe2x80x9d, comprising an address block and a control block, a xe2x80x9cpayloadxe2x80x9d or data block that is the actual data to be transferred from endpoint to endpoint, and a CRC error correction block.
The need for higher speed communication protocols that are less susceptible to switching delays has led to the development of the asynchronous transfer mode (ATM) telecommunications standard. ATM was originally intended as a service for the broadband public telephone network. Although designed primarily for the high-speed transfer of video and multimedia information, the most popular applications for ATM so far have been data transmission. ATM switches are widely used as the backbone of large business networks and in wide area networks.
ATM provides speeds from 50 Mbps up to 10 Gbps using fast packet switching technology for high performance. ATM uses small fixed-size packets, called xe2x80x9ccellsxe2x80x9d. A cell is a 53-byte packet comprising 5 bytes of header/descriptor information and a 48-byte payload of voice, data or video traffic. The header information contains routing tags and/or multi-cast group numbers that are used to configure switches in the ATM network path to deliver the cells to the final destination.
ATM is a relatively new technology and currently represents only a comparatively small percentage of the installed network infrastructure. Frame relay still remains as a dominant portion of the installed network infrastructure. Additionally, since many information systems may never need video or other high bandwidth applications, it is unlikely that every LAN or WAN system will need to be converted to an ATM system. Hence, frame relay and ATM will likely coexist for a long period of time.
In order to allow frame relay systems and ATM systems to communicate with one another, a host of well-known interfaces have been developed to interconnect frame relay based networks with ATM based networks. These frame relay-to-ATM interfaces typically include high-level data link control (HDLC) interfaces for sending and receiving frames from frame relay-based networks/devices and segmentation and reassembly (SAR) interfaces for sending and receiving cells from ATM networks/devices.
ATM switches and frame relay switches use multiple data processors to transfer and process data frames and ATM cells and to provide the power needed to handle very large data traffic loads. These data processors are frequently implemented in hierarchical architectures wherein one processor, frequently referred to as xe2x80x9cmasterxe2x80x9d processor or xe2x80x9cprimaryxe2x80x9d processor, controls the operations of one or more other processors, frequently referred to as xe2x80x9cslavexe2x80x9d processors or xe2x80x9csecondaryxe2x80x9d processors.
Typically, the primary data processor sends data and/or assigns tasks to the secondary data processors in order to distribute work evenly and accomplish parallel processing. This leads to higher throughput rates. In general, the primary processor controls the initialization and operation of each of the secondary processors. The primary processor can control the operation of a secondary processor by loading the memory used by the secondary processor with data and applications selected by the primary processor.
For example, a frame-relay interface unit (FIU) in an ATM switch may contain a master processor that controls a group of protocol conversion circuit cards (e.g., frame relay-to-ATM converters), each of which contains a slave processor that receives instructions from the master processor. During a boot-up operation, the master processor may execute its own self-test program by reading a self-test program from a ROM associated with the primary processor. After the primary processor validates itself, the primary processor may load application programs into the RAM memories used by the slave processors to cause each slave processor to process data traffic.
There are problems inherent in this type of multiprocessor architecture, however. For example, in the ATM switch FIU described above the secondary processors do not have the ability to validate their own operation in a self-test mode, since the secondary processors are dependent on the primary processor for control. Thus, the secondary processors must be operational without first being tested. If a failure does occur in a secondary processor, it must be debugged in a time consuming process by the primary processor or by special purpose emulation hardware that tests the slave processor separately. Furthermore, as a practical consideration, the debug program for a secondary processor is not stored in the (relatively) small local memory used by the primary processor. Instead, the primary processor retrieves the debug program for the secondary processor from an external source, such as a memory located else where in the ATM switch. If however, the device in which the primary and secondary processors are located is not coupled to the external source, then the secondary processors cannot be tested at all.
There is therefore a need in the art for multiprocessor systems that provide improved circuits and methods for validating the operation of slave processors controlled by a master processor. In particular, there is need for an improved multiprocessor system wherein a master processor can direct a slave processor to operate in a test mode, wherein the slave processors validates itself, or in a system mode, wherein the slave processor executes programs and processes data received from the primary processor.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a data processing device containing a first processor and a second processor controllable by the first processor, a mode selection circuit capable of selecting an operating mode of the second processor comprising: 1) a mode determination circuit capable of determining a current operating mode of the first processor; and 2) a mode control circuit coupled to the mode determination circuit capable of causing the second processor to operate in a first selected operating mode.
According to one embodiment of the present invention, the second processor is coupled to a read-only memory (ROM) capable of storing a test program operable to test the second processor and a random-access memory (RAM) capable of storing an application program.
According to another embodiment of the present invention, the mode control circuit causes the second processor to execute the test program in the ROM in response to a determination by the mode determination circuit that the first processor is in a test mode.
According to yet another embodiment of the present invention, the mode control circuit causes the second processor to execute the application program in the RAM in response to a determination by the mode determination circuit that the first processor is in a system mode wherein the first processor processes data traffic under control of an application program.
According to still another embodiment of the present invention, the mode control circuit is a switch capable of coupling the ROM to data paths of the second processor.
According to a further embodiment of the present invention, the mode control circuit is a switch capable of coupling the RAM to data paths of the second processor.
According to a still further embodiment of the present invention, the mode determination circuit determines the current operating mode in response to an interrupt signal received from the first processor.
According to a yet further embodiment of the present invention, the mode determination circuit determines the current operating mode in response to a power reset signal received from the data processing device.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.